MPhil Thesis Defence


"PACKET SCHEDULING ALGORITHMS FOR VIRTUAL OUTPUT QUEUED SWITCHES"

By

Miss Ying Jiang


Abstract

The past few years have seen increasing interest in arbitrary topology
cell-based local area networks, such as ATM. In these networks, hosts are
connected together by an arbitrary graph of communication links and
switches. They offer a number of potential advantages relative to other
approaches. However to realize these potential advantages, a high
performance router or switch is needed to take data arriving on an input
link and quickly deliver it to the appropriate output link. In this
thesis, we consider switches dealing with fixed-length packets, or cells.

We explore the basic architecture of routers and different types of switch
fabrics. According to the relative speed of the input ports and the switch
fabric, a switch can be classified as input queued (IQ), output queued
(OQ) or combined input and output queued (CIOQ). IQ switches have
attracted more attention because of low hardware requirement. Virtual
Output Queuing (VOQ) is a method to solve the HoL problem of IQ switches
and is a practical and high-performance packet switch architecture.

We propose two unicast scheduling algorithms for the VOQ architecture
switches and a new architecture and its corresponding scheduling algorithm
to handle multicast traffic. We also consider how to integrate them in
order to process the real-life traffic composed of both unicast and
multicast packets. In order to provide QoS scheduling based on our
algorithms, we propose a buffer management method which can be used on
input queues to provide fair share of resources among different flows.


Date:			Wednesday, 8 August 2001

Time:			10:00a.m.-12:00noon

Venue:			Room 1505
			Lifts 25-26

Committee Members:	Dr. Mounir Hamdi (Supervisor)
			Dr. Brahim Bensaou (Chairman)
			Dr. Jogesh Muppala


**** ALL are Welcome ****