PhD Qualifying Examination


"Scalable packet switches based on shared memory
architecture"

By Mr. Feng Wang


Abstract:

Shared memory architectures are thought to be unsuitable for building high
performance switches/routers. The main reason lies in their perceived poor
scalability. In particular, shared memory architectures are typically used
to build output-queued switches which are regarded as the best candidate
to achieve optimal delay-throughput performance. The current trend in
router/switch design in both industry and academia favors crossbar-based
architectures with VOQ techniques because they provide a scalable
solution. Although shared memory architectures seem to have the obvious
scalability disadvantage, crossbar-based architectures have their own
intrinsic complex scheduling algorithms and higher bandwidth allocation
compared with shared memory architectures of the same capacity. In this
urvey, we investigate the problem of shared memory design in detail and
try to find alternatives to solve the scalability bottleneck. In the end,
we show that combining crossbar and shared memory architecture is the most
promising method for building scalable high performance switches/routers
that can provide quality-of-service support.


Date:     		Wednesday, 26 January 2005

Time:                   10:30a.m.-12:30p.m.

Venue:                  Room 2504
			lifts 25-26

Committee Members:      Prof. Mounir Hamdi (Supervisor)
			Dr. Jogesh Muppala (Chairperson)
			Dr. Brahim Bensaou
			Dr. Gary Chan


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