Building Scalable Next Generation Internet Routers

The Hong Kong University of Science and Technology
Department of Computer Science and Engineering


PhD Thesis Defence


Title: "Building Scalable Next Generation Internet Routers"

By

Mr. Feng Wang


Abstract

With the constantly growing Internet traffic and development of broadband 
access technologies such as DSL, cable modem, and gigabit Ethernet, future 
broadband packet switches/routers should be able to support a large number of 
connection ports for at least the following two reasons: a) the number of 
Internet access points is still rapidly increasing; and b) the development of 
optical transmission technologies makes huge number of communication channels 
available. Both facts impose a challenge on the router's scalability with 
regard to the increasing number of network flows and switching ports. In 
addition, routers are also required to be able to provide Quality-of-Service 
(QoS) at the surge of triple-play services (data, voice and video) in 
Next-Generation-Networks (NGN).  In this thesis, we try to address this 
switching ports scalability issue and design the routers with QoS support as 
well.

The two main router components we are investigating are: the switch fabric and 
the memory subsystem. We start from the Space-Memory-Space switch design 
paradigm that is proven to provide QoS relatively easily, and then use the 
Clos-interconnection to scale its space parts. By making all packet buffers 
fully shared (in a distributed way), we show that the Central-stage Buffered 
Clos-network (CBC namely) are scalable in terms of not only the hardware cost, 
but the complexities of scheduling algorithms as well. To scale the router's 
memory subsystem, we introduce parallelism into current SRAM/DRAM combination 
solutions and design a Parallel Hybrid SRAM/DRAM (PHSD namely) memory system. 
By simple yet efficient memory management algorithms, we show that the PHSD can 
significantly outperform previous solutions by reducing both the packet delay 
and the costly requirement on SRAM.


Date:			Wednesday, 15 October 2008

Time:			10:30a.m.-12:30p.m.

Venue:			Room 4480
 			Lifts 25-26

Chairman:		Prof. Ravindra Goonetilleke (IELM)

Committee Members:	Prof. Mounir Hamdi (Supervisor)
 			Prof. Mordecai Golin
 			Prof. Qian Zhang
 			Prof. Chi-Ying Tsui (ECE)
 			Prof. Hussein Mouftah (Inf. Tech. & Engg.,
 						Univ. of Ottawa)


**** ALL are Welcome ****