VEX: A zkRollup Architecture for Verifiable Exchange Systems

The Hong Kong University of Science and Technology
Department of Computer Science and Engineering


MPhil Thesis Defence


Title: "VEX: A zkRollup Architecture for Verifiable Exchange Systems"

By

Mr. Xiangan TIAN


Abstract:

Non-custodial on-chain trading platforms are fundamental to decentralized 
finance (DeFi), enabling transparent asset exchanges while allowing users to 
retain direct control over their funds. However, scalability challenges on 
Layer 1 (L1) blockchains have driven the adoption of Layer 2 (L2) solutions, 
particularly zero-knowledge rollups (zkRollups). Despite their scalability 
benefits, zkRollups face significant computational bottlenecks during proof 
generation, resulting in high hardware costs and prolonged processing times.

This thesis introduces VEX, an application-specific zkRollup architecture 
optimized for verifiable exchange systems. To address the computational 
inefficiencies in zkRollup proof generation, we propose two key 
optimizations: (1) PLONK with Segment Lookup: By enabling the selective 
activation of transaction-type-based sub-circuits rather than processing an 
entire monolithic circuit, the prover's computational cost scales only with 
active sub-circuits. This eliminates the inefficiency of evaluating inactive 
transaction paths; and (2) Shared Logic Offloading: Common computations 
across transaction types, such as signature and hash verification, are 
decoupled from transaction-specific logic. These shared operations are 
precomputed and proven separately, reducing overhead for segment lookup and 
allowing fine-grained optimizations tailored to repetitive tasks. The proof 
components from shared logic and transaction-specific logic are subsequently 
aggregated using a CP-SNARK construction. To facilitate efficient CP- SNARK 
construction with universal and updatable SRS, we propose a novel linking 
protocol featuring constant proof size and verification time. We evaluate 
the VEX architecture across essential transaction workflows, demonstrating 
substantial improvements in proof generation efficiency and scalability 
compared to monolithic circuit designs.


Date:                   Tuesday, 21 January 2025

Time:                   10:00am - 12:00noon

Venue:                  Room 5501
                        Lifts 25/26

Chairman:               Prof. Cunsheng DING

Committee Members:      Dr. Dimitris PAPADOPOULOS (Supervisor)
                        Prof. Ke YI