Machine Learning for Logic Synthesis of VLSI Circuits

PhD Thesis Proposal Defence


Title: "Machine Learning for Logic Synthesis of VLSI Circuits"

by

Mr. Dimitrios TSARAS


Abstract:

Logic synthesis is a central step of chip design, turning a register-transfer
level description into an optimized gate-level netlist. As designs grow to
billions of gates, a single synthesis run can take days, and because engineers
iterate several times to meet their targets, synthesis runtime has become a
major part of design turnaround time. Two directions can reduce it: partitioning
large designs so that their parts are synthesized in parallel without degrading
the result, and making the optimization within each part more efficient.

Machine learning can support both, by predicting synthesis behavior from earlier
runs and by proposing optimizations directly, but synthesis must preserve the
circuit's function exactly. A learned model is therefore useful only if its
mistakes cost runtime or quality, never correctness.

In this thesis, I present four methods that follow this principle. PP2Tree
predicts module-level synthesis workloads, partitioning the hierarchy to balance
the parallel schedule against each cut's quality cost, halving parallel
synthesis time versus a tuned partitioner. ELF, observing that most refactoring
attempts bring no improvement, predicts and skips them, speeding up refactoring
severalfold with negligible area loss. ShortCircuit, an AlphaZero-trained
transformer, generates And-Inverter Graphs from truth tables, beating ABC's
direct construction. DeepResub brings such generation into resubstitution,
verifies every replacement exactly, and improves 63 best-known IWLS contest
results.

A recent trend in electronic design automation uses large language models
directly to write and debug RTL or even drive the design flow. These models
struggle with rare domain vocabulary and long inputs. I target both with two
methods, evaluated on general-domain benchmarks. GEM, a pretraining regularizer
pulling hidden states toward predicted-token embeddings, lowers perplexity and
makes intermediate layers more decodable. HASA, a sparse attention operator
reading each context span at query-dependent resolution, outscores full
attention on LongBench while attending to about a quarter of cached entries.


Date:                   Monday, 2 November 2026

Time:                   2:00pm - 4:00pm

Venue:                  Room 3494
                        Lifts 25/26

Committee Members:      Prof. Dimitris Papadias (Supervisor)
                        Dr. Zhiyao Xie (Co-supervisor, ECE)
                        Prof. Raymond Wong (Chairperson)
                        Dr. Dimitris Papadopoulos