Efficient Application Mapping and Scheduling for Networks-on-Chip

PhD Qualifying Examination


Title: "Efficient Application Mapping and Scheduling for Networks-on-Chip"

Mr. Weichen Liu


Abstract:

Networks-on-Chip (NoC) is recently proposed as an alternative to the
on-chip bus to meet the increasing requirement of complex
communication needs in Systems-on-Chip (SoC). In embedded systems
design with NoC technology, real-time performance and power
dissipation are the main concerns. A common workflow of an
application-specific networks-on-chip design includes network
topology synthesis, communication channel width and buffer size
selection, IP core mapping, packets routing and switching, and
real-time scheduling of the task executions and communications. The
optimization of these interacting factors plays an important role in
the quality of the NoC system design. Many techniques in traditional
networking research can be adapted and applied to NoC, but NoC also
brings with its own unique set of research challenges. In this
report, I survey the current advances on some challenging issues in
design space exploration of efficient NoC designs, especially on the
application mapping and scheduling problems. For comparison, related
techniques for bus-based SoCs in literature are also presented.


Date:     		Friday, 18 April 2008

Time:                   10:30a.m.-12:30p.m.

Venue:                  Room 3304
			lifts 17-18

Committee Members:      Dr. Zonghua Gu (Supervisor)
			Dr. Jogesh Muppala (Chairperson)
			Prof. Mounir Hamdi
			Dr. Jiang Xu (ECE)


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