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Design and Optimization of High-Performance Resilient Network-on-Chip Based Multiprocessor System-on-Chip
PhD Thesis Proposal Defence
Title: "Design and Optimization of High-Performance Resilient Network-on-Chip
Based Multiprocessor System-on-Chip"
by
Mr. Weichen Liu
ABSTRACT:
As feature sizes continue to shrink with the advancement of
nanotechnology, multiprocessor system-on-chip (MPSoC) becomes a promising
solution to satisfy the growing demands of future complex applications.
Network-on-chip (NoC) can effectively improve the scalability and lower
the power consumption of MPSoC, and it is replacing traditional bus as the
major MPSoC communication architecture. In this proposal, I study
NoC-based MPSoC design and optimization methods to improve MPSoC
performance and reliability. Given an MPSoC application and hardware
architecture, the challenges are mapping the application tasks onto
available processor cores, scheduling the task executions, and allocating
memory resources to the application tasks to optimize system performance
and hardware utilization. Formal methods, including satisfiability (SAT),
satisfiability modulo theories (SMT) and model checking (MC), are studied,
and sophisticated search space reduction techniques are proposed to
significantly improve the performance. The proposed techniques are applied
to a novel NoC-based MPSoC architecture, called sensor-network-on-chip
(SENoC). SENoC can collaboratively monitor the chip reliability and
guarantee correct and efficient executions of MPSoC applications under
soft errors and power gating induced power/ground noises. To facilitate
NoC-based MPSoC evaluations, I develop a benchmark suite based on
realistic MPSoC applications.
Date: Tuesday, 3 May 2011
Time: 10:30am - 12:30pm
Venue: Room 4483
lifts 25/26
Committee Members: Dr. Jogesh Muppala (Supervisor)
Dr. Jiang Xu (Supervisor, ECE)
Dr. Qiong Luo (Chairperson)
Dr. Charles Zhang
Prof. Chin-Tau Lea (ECE)
**** ALL are Welcome ****