Survey on Combinational Logic Optimization

PhD Qualifying Examination


Title: "Survey on Combinational Logic Optimization"

by

Mr. Dimitrios TSARAS


Abstract:

The rapid proliferation of AI and expanding technological infrastructure has 
triggered an unprecedented surge in computational demands, far exceeding the 
capabilities of existing hardware and creating a critical bottleneck to their 
continued advancement. This highlights the need for improved chip design 
flows where at the core lies combinational logic optimization. Logic 
optimization is the process of transforming digital circuits into 
functionally equivalent yet smaller, faster, or more energy-efficient forms. 
Despite its fundamental importance, the literature on this subject has become 
increasingly fragmented across different research communities and 
optimization paradigms. This comprehensive survey aims to systematically 
categorize optimization techniques based on their underlying netlist 
representations (including And-Inverter Graphs, XOR-And-Inverter Graphs, and 
Majority-Inverter Graphs) and the core optimization methods they employ. 
Additionally, we explore emerging approaches leveraging machine learning 
techniques that promise to enhance traditional optimization flows through 
intelligent algorithm selection and parameter tuning. Finally, we identify 
critical gaps in the current literature and propose future research 
directions to address scalability challenges and potential improvements in 
the quality of results for next-generation computing systems.


Date:                   Wednesday, 23 April 2025

Time:                   10:30am - 12:30pm

Venue:                  Room 4475
                        Lifts 25/26

Committee Members:      Prof. Dimitris Papadias (Supervisor)
                        Dr. Zhiyao Xie (Co-supervisor, ECE)
                        Prof. Raymond Wong (Chairperson)