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Interconnection Networks and Packet Buffer Architectures for Massive Data Centers
PhD Thesis Proposal Defence Title: "Interconnection Networks and Packet Buffer Architectures for Massive Data Centers" by Mr. Dong LIN ABSTRACT: Massive data centers are being built around the world to provide various cloud computing services. As a result, data center networking has recently been a hot research topic in both academia and industry. A fundamental challenge in this research is the design of the data center network that interconnects the massive number of servers, and provides efficient and fault-tolerant routing service to upper-layer applications. In response to this challenge, the research community have begun exploring novel interconnect topologies. One approach is to use commodity switches or servers to scale out the network, such as Portland, VL2, DCell, BCube and FiConn. The other approach is to exploit optical devices to build high-capacity switches, such as Helios, HyPaC, PETASW, Data Vortex and OSMOSIS. Understandably, this research is still in its infancy. For the first approach, the proposed solutions either scale too fast (i.e., double exponentially) or too slow, suffer from performance bottlenecks, or can be quite costly. For the second approach, where the entire interconnection network can be regarded as a “giant” switch, its performance heavily relies on well-designed packet buffers that support multiple queues, provide large capacity and short response time. In this proposal, five different kinds of algorithms/architectures are presented, addressing on both of these issues respectively. Using small-port-count commodity switches, I propose two cost-effective and gracefully scalable Data Center Interconnects (DCIs) called Hyper-BCube and LacoNet that combine the advantages of both DCell and BCube architectures while avoiding their limitations. On the other hand, aiming at scalable packet buffers, I propose three memory management algorithms along with their architectures termed Radom-Round-Robin, distributed and hierarchical schemes. Preliminary experimental results show that these schemes can outperform the traditional algorithms significantly in terms of low time complexity, short access delay and guaranteed performance. My future work will be carried out along following directions. First, I will conduct more experiments and simulations to comprehensively evaluate the performance of the proposed algorithms/architectures in different settings and environments. Second, the fault-tolerant and load-balancing routing algorithms for the proposed DCIs are still required to be further investigated. Date: Tuesday, 21 June 2011 Time: 10:00am - 12:00noon Venue: Room 4475 lifts 25/26 Committee Members: Prof. Mounir Hamdi (Supervisor) Dr. Brahim Bensaou (Chairperson) Dr. Lin Gu Dr. Jogesh Muppala **** ALL are Welcome ****