A Survey on In Memory Parallel Joins on Heterogeneous processors

PhD Qualifying Examination


Title: "A Survey on In Memory Parallel Joins on Heterogeneous processors"

by

Mr. Hao LIU


Abstract:

Modern computer processors have become massively parallel and highly heteroge- 
neous. The spectrum includes multi-core CPUs of tens of powerful cores, 
many-core co-processors of a few tens of less powerful cores, Graphics 
Processing Units (GPUs) of hundreds to thousands of lightweight cores, 
Accelerated Processing Units (APUs) of heterogeneous processors on a single 
chip, and Field Programmable Gate Arrays (FP- GAs) of congurable assembly of 
logic gates. Such diverse processor architectures call for innovations and 
optimizations in software systems to achieve a high performance.

In this survey, we study in-memory parallel join algorithms for heterogeneous 
pro- cessors. Join is the central operator in database systems, and there have 
been intensive studies on various join algorithms, both in-memory and 
out-of-core. Two main join algorithms are hash join and sort-merge join. On the 
CPU, both algorithms have their hardware-oblivious and hardware-conscious 
variants. In contrast, on the other processors, both join algorithms are 
designed and implemented in full consideration of the processor as well as 
memory hierarchy characteristics. Additionally, we survey window-based stream 
join algorithms on these architectures.


Date:			Friday, 12 June 2015

Time:                  	11:30am - 1:30pm

Venue:                  Room 4483
                         Lifts 25/26

Committee Members:	Prof. Lionel Ni (Supervisor)
 			Dr. Lei Chen (Chairperson)
 			Dr. Lin Gu
 			Dr. Qiong Luo


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