High-performance Hardware-accelerated Datacenter Systems

PhD Thesis Proposal Defence


Title: "High-performance Hardware-accelerated Datacenter Systems"

by

Mr. Chaoliang ZENG


Abstract:

In recent decades, we have witnessed extensive construction of datacenters and 
widespread deployments of various applications. There are two emerging trends 
in datacenter application and hardware infrastructure, respectively. On the 
application side, with the rapid rise of Internet services and cloud computing, 
application demands keep increasing, which are close to or even faster than 
Moore's law. Therefore, it is hard to meet the ever-growing system demands by 
only upgrading hardware infrastructure, and critical to make 
application-oriented optimization. On the hardware side, besides 
general-purpose processors, modern datacenters have deployed many types of 
domain-specific processors, e.g., FPGA, TPU, programmable switch, and even 
customized ASIC, which provide an ample architecture design space for 
application systems. Given the above emerging trends in datacenter systems, we 
believe a high-performance application system should consider optimizations on 
both software algorithm and hardware architecture.

This thesis describes my research efforts in building high-performance 
datacenter systems with hardware acceleration. Specifically, we design two 
types of domain-specific accelerators for networking and computation, 
respectively.

Regarding networking, we design Tiara, a three-tier hardware architecture to 
accelerate stateful layer-4 load balancing. Tiara makes the best use of 
heterogeneous hardware by decoupling the load balancing function. As a result, 
Tiara can provide high performance with cost, energy, and space efficiency. We 
believe Tiara three-tier architecture is generic and can benefit more 
datacenter gateway functions.

Regarding computation, we study the embedding-based retrieval algorithm from 
the first principles and derive a practically ideal architecture for the 
optimal performance. Based on the derived architecture, we propose FAERY for 
high-performance embedding-based retrieval running on FPGA. FAERY leverages 
appropriate parallel techniques to orchestrate key operators in embedding-based 
retrieval, so that FAERY can outperform CPU- and GPU-based approaches. Although 
FAERY is a DSA for retrieval in recommendation systems, we believe similar 
optimization techniques can be applied to systems bounded by memory and 
computation.

Besides the above designs, we discuss some potential directions that can be 
explored in the future. For example, as an extension of Tiara, how to adopt a 
similar three-tier architecture to IPSec gateway to provide high scalability 
for cross-region communications in edge computing and content delivery 
networks?


Date:			Wednesday, 17 August 2022

Time:                  	4:00pm - 6:00pm

Zoom Meeting: 
https://hkust.zoom.us/j/95850251147?pwd=SU4xZUJLVmJ5Qmd5MVVFRzRicUw1QT09

Committee Members:	Prof. Kai Chen (Supervisor)
 			Dr. Wei Wang (Chairperson)
 			Prof. Bo Li
 			Dr. Yangqiu Song


**** ALL are Welcome ****