DPU-Accelerated Host Networking Towards 100Gbps+ Ethernet: A Systematic Survey

PhD Qualifying Examination


Title: "DPU-Accelerated Host Networking Towards 100Gbps+ Ethernet: A 
Systematic Survey"

by

Mr. Xinyang HUANG


Abstract:

The emergence of Data Processing Units (DPUs), i.e., network interface cards 
with programmable logic, multi-core processors, and on-board accelerators, 
has transformed the architecture of high-performance networked systems. This 
survey presents a structured taxonomy of DPU-accelerated host networking 
systems, categorizing recent research along three principal axes: 
architecture re-design, NIC infrastructure evolution, and operating system 
support. We analyze key trends in how computation is offloaded---from 
functional partitioning to efficient I/O---and how NICs evolve in queue 
density, programmability, multiplexing, and isolation. We also examine the 
growing role of NIC-aware OS, including heterogeneous abstractions, offload 
frameworks, and scheduling mechanisms. We elaborate on the trends that led to 
the emergence of this technology and highlight the most important pointers 
from the literature.


Date:                   Tuesday, 29 July 2025

Time:                   1:00pm - 3:00pm

Venue:                  Room 3494
                        Lifts 25/26

Committee Members:      Prof. Kai Chen (Supervisor)
                        Dr. Xiaomin Ouyang (Chairperson)
                        Prof. Gary Chan