Network Processors: A Solution to the Next Generation Networking Challenges

Speaker:	Professor Laxmi Narayan Bhuyan
		Department of Computer Science and Engineering
		University of California, Riverside

Title:		"Network Processors: A Solution to the Next
		 Generation Networking Challenges"

Date:		Tuesday, 12 September 2006

Time:		4:00pm - 5:00pm

Venue:		Room 2404  (via lift nos. 17/18)
		HKUST

ABSTRACT:

Network processors (NPs) are programmable on-chip devices that can provide
high-throughput packet processing using multithreaded shared memory
multiprocessor architectures. They are flexible like general-purpose
processors, but provide high performance like ASICs. At the same time,
they can be employed at the link layer thus avoiding the high protocol
stack overhead in operating systems. This talk will present possible
future deployment of NPs in many applications like building firewalls,
home computing, multimedia transcoding, and wireless and sensor networks.

This talk will also present the analysis, design and implementation of a
content aware switch in our laboratory based on an IXP2400 network
processor (NP). Content aware switches can examine web requests and
distribute them to the web servers based on application level information.
We explore various design tradeoffs, develop an NP-Splice protocol, and
implement various tasks in the processors. Measurement results based on an
IXP 2400 NP demonstrate that our NP-based switch can reduce the http
processing latency by an average of 83.3% for a 1K byte web page, compared
to a Linux-based switch. The amount of reduction increases with larger
file sizes. It is also shown that the packet throughput can be improved by
up to 5.7 times across a range of files.


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Biography:

Laxmi Narayan Bhuyan is a professor of Computer Science and Engineering at
the University of California, Riverside since January 2001. Prior to that
he was a professor of Computer Science at Texas A&M University (1989-2000)
and Program Director of the Computer System Architecture Program at the
National Science Foundation (1998-2000). He has also worked as a
consultant to Intel and HP Labs. Dr. Bhuyan received his Ph.D. degree in
Computer Engineering from Wayne State University in 1982. His current
research interests are in the areas of network computing, multiprocessor
architectures, router and web server architectures, parallel and
distributed processing, and performance evaluation. He has published more
than 150 papers in these areas in IEEE Transactions on Computers (TC),
IEEE Transactions on Parallel and Distributed Systems (TPDS), Journal of
Parallel and Distributed Computing (JPDC), and many refereed conference
proceedings.

Dr. Bhuyan currently serves as the Editor-in-Chief of the IEEE
Transactions on Parallel and Distributed Systems (TPDS). He is a past
Editor of the IEEE TC, JPDC, and Parallel Computing Journal. His
professional activities are too numerous to describe. To mention a few, he
was the founding Program Committee Chairman of the HPCA in 1995, Program
Chair of the IPDPS in 1996, General Chair of ADCOM-2001, and General Chair
of HPCA-9 (2003). He was elected Chair of the IEEE Computer Society
Technical Committee on Computer Architecture (TCCA) between 1995-1998.

Dr. Bhuyan is a Fellow of the IEEE, a Fellow of the ACM, a Fellow of the
AAAS (American Association for the Advancement of Science), and a Fellow
of the WIF (World Innovation Foundation). He has also been named as an ISI
Highly Cited Researcher in Computer Science. He has received other awards
such as Halliburton Professorship at Texas A&M University, and Senior
Fellow of the Texas Engineering Experiment Station. He was also awarded
the IEEE CS Outstanding Contribution Award in 1997.