Parallel Programming Environment: A key to translate tera-scale platforms into a big success

Speaker:	Dr. Jesse Fang
		Sr. Principal Engineer
		Director of Programming System Lab
		Intel/CTG

Title:		"Parallel Programming Environment: A key to translate
		 tera-scale platforms into a big success"

Date:		Wednesday, 24 January 2007

Time:		2:30pm - 3:30pm

Venue:		Room 1505 (near lift nos. 25/26)
		HKUST

Abstract:

Moore's Law will continue in couple decades. The silicon technology is
moving from 90nm to 65nm in 2006, and will continue to move to 45nm, 32nm
and 22nm in future. With 22nm technology, we will have more than 32Billion
transistors on a die. But the power and thermal constraints limit the
frequency increased. In that way, multi-core or many-core will be the way
of the future microprocessor design. HW is moving faster than SW expects.
The major microprocessor vendors provided dual-core product in 2006, and
will have quad-core product or even more-cores on die soon.

In the near future, HW platform will have many-cores (>16 cores) on die.
Its computation capability will be more than 1 TIPs (Tera Instructions Per
Second). These cores will have their own local fast cache and larger but a
little slow shared on-die cache. They will communicate each other through
on-die interconnect fabric with >1 TB/s on-die bandwidth and <30 cycles
on-die latency. The HW system with TIPs of compute power operating in
Tera-bytes of data and with great scalability is called "Tera-scale"
platform. We may have such Tera-scale system in our desk-top or lap-top in
a few years.

Now, let's turn to SW areas, especially the SW implications with the HW
changes from uniprocessor to Tera-scale platform with many-cores as "the
way of the future". Multi/many-core platform will benefit concurrent
coarse-grained applications in server. It may help certain application
domains in client like graphics, game and multimedia. It will be great
challenge for programming environment to help programmers to develop
concurrent code for the most main-stream client software. A lot of issues
are still open to the language/compiler/runtime research community.

As research results showed in the past couple decades, the general purpose
parallel programming is difficult. It's possible that different
applications require different concurrent programming environment.
However, a good concurrent programming environment should extend the
existing programming languages for most of typical programmers who are
familiar with. These extensions must bring benefits for concurrent
programming, which open a lot of the new research topics. This talk will
cover those interesting research topics in such tera-scale multi-core
platforms.


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Biography:

Jesse Fang is Director and Chief Scientist of Programming System Lab at
Intel/CTG (Corp. Technology Group). Jesse created the lab about 11 years
ago, and has been leading the lab to develop programming environment
technologies to enable Intel HW uArch research and microprocessor design,
and transfer SW technologies to Intel Software Solution Group. Before
joined Intel in 1995, Jesse was manager of compiler at Hewlett-Packet
Research Lab to initiate Itanium Architecture since 1991. Jesse ran a
small start-up between HP and Intel. Before HP Labs, Jesse was working as
manager or technical leader on parallel/vector compiler in Convex and
Concurrent Computer Corp. respectively from 1989 and 1986. Jesse Fang got
his Ph.D. in Computer Science at University of Nebraska-Lincoln before he
did post-Doctor at University of Illinois Urbana-Champaign. He was
Associate Professor at University of Kansas before moved to industry.
Jesse got his B.S. in Math at Fudan University in Shanghai.